Hardware Validation Engineer

Naga Nanda Sai Palanki

I bring up new silicon, validate its interfaces and automate the testing, from first power-on through production sign-off.

Desktop
Austin

BenchOS

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Open to new roles

Every new chip has to prove itself on the bench. That proof is my work.

I am a Hardware Validation Engineer with 3+ years of hands-on experience in post-silicon bring-up, peripheral and protocol validation, and system-level hardware qualification.

At Microchip Technology in Austin, I validate PCIe Gen4 and peripheral interfaces, automate lab testing and support qualification. Before that, I spent nearly two years on peripheral validation at STMicroelectronics in Bangalore. When something fails, I work with firmware, design and platform teams to find the root cause.

Also known as Nandu.

Based in
Austin, TX
Now
Microchip Technology
Before
STMicroelectronics
Education
M.S. Computer Science, University of North Texas
B.Tech ECE, Lakireddy Bali Reddy College of Engineering
Open resume

3+ years in post-silicon validation.

REV B · Jul 2025 – Present

Microchip Technology

Hardware Validation Engineer, Austin, TX
  • Performed post-silicon board bring-up on evaluation platforms, including power sequencing, clock validation and debug connectivity checks.
  • Validated PCIe Gen4 link behavior, including link training, LTSSM state transitions and ASPM power states, across endpoint device types including storage controllers and connectivity chips.
  • Executed functional and regression testing on I2C, SPI, UART and GPIO interfaces, including fault and error-injection scenarios.
  • Used oscilloscopes, logic analyzers, protocol analyzers and DMMs to investigate and debug interface and signal-level failures.
  • Developed Python and Bash scripts on Linux to automate test execution, control lab instruments via VISA, collect diagnostics and compare results across silicon revisions.
  • Reproduced and root-caused test failures, capturing waveforms and register-state data with firmware and design teams to drive hardware bug resolution.
  • Supported EVT, DVT and PVT qualification using thermal chambers and voltage margin tools, validating hardware stability across full temperature and voltage operating ranges for production sign-off.
REV A · Aug 2021 – Jun 2023

STMicroelectronics

Hardware Validation Engineer, Bangalore, India
  • Validated I2C, SPI and UART/USART peripheral interfaces across multiple operating modes and configurations.
  • Tested UART in polling, interrupt and DMA transfer modes across varying baud rates, verifying framing, parity and overrun error recovery.
  • Supported board bring-up, including power rail checks, oscillator and PLL behavior, clock distribution and SWD/JTAG debug connectivity.
  • Captured and analyzed I2C, SPI and UART waveforms, comparing register states to isolate firmware, configuration, board or silicon-level issues.
  • Developed Python, Bash and Embedded C scripts on Linux to automate validation and regression testing, and analyzed failure logs for recurring defect patterns across successive silicon tape-outs.

My work, laid out like a die.

Select a block to inspect it.

  • Microchip Technology

    PCIe Gen4 link validation

    Validated link training, LTSSM state transitions and ASPM power states across endpoint device types, including storage controllers and connectivity chips.

  • Microchip Technology and STMicroelectronics

    Lab automation

    Built Python and Bash scripts on Linux that execute tests, control lab instruments over VISA, collect diagnostics and compare actual against expected results across silicon revisions.

  • Microchip Technology and STMicroelectronics

    Board bring-up

    Brought up evaluation platforms through power sequencing and rail checks, clock, oscillator and PLL behavior, and SWD/JTAG debug connectivity.

  • STMicroelectronics

    UART validation across modes

    Tested polling, interrupt and DMA transfer modes across varying baud rates, verifying framing, parity and overrun error recovery.

  • Microchip Technology and STMicroelectronics

    Root-cause debug

    Captured waveforms and register state with oscilloscopes, logic analyzers and protocol analyzers to isolate firmware, configuration, board or silicon-level issues.

  • Microchip Technology

    Production qualification

    Supported EVT, DVT and PVT testing with thermal chambers and voltage margin tools, validating hardware stability across full temperature and voltage operating ranges.

Installed skills.

Protocols
PCIe Gen4LTSSMLink trainingASPMNVMeI2CSPIUART/USARTGPIO
Validation
Board bring-upPower sequencingClock and PLL validationFunctional testingRegression testingFault injectionPVT margin testingEVT/DVT/PVTServer platform qualification
Lab equipment
OscilloscopesLogic analyzersProtocol analyzersDMMsThermal chambersPower suppliesST-Link/SWDJTAG debuggers
Automation
PythonInstrument controlLog parsingBashEmbedded CLinux CLI
Also
Root-cause analysisJIRARegister-level datasheet compliance
Received- Bit time- Frame time-

A working UART decoder, reading this waveform bit by bit. Set parity to None with a flipped bit, and the wrong character gets through with no error.

guest@bench:~$

Open to new roles

Have a chip that needs proving?

Email is the best way to reach me about hardware validation roles.

nandasaipalanki9@gmail.com
LinkedIn Open resume

When the lab is quiet.

Gaming
GTA V on PC and PS5, and Mortal Kombat. I grew up playing Vice City.
Movies
Telugu cinema, especially Pawan Kalyan films like Jalsa, Kushi and Gabbar Singh.
Languages
Telugu (native), English, and Hindi, which I am working on.

0 items.

Every failure that landed here has been root-caused.